►书籍章节
[1]H. Jiaoand V. Kursun, “Tri-Mode Operation for Noise Reduction and Data Preservation in Low-Leakage Multi-Threshold CMOS Circuits,”VLSI-SoC: Forward-Looking Trends in IC and System Design, J. L. Ayala, D. A. Atienza, and R. Reis, (Eds.), Springer, pp. 258-290, 2012, ISBN 978-3-642-28565-3.
►期刊论文 (* Corresponding author; ^ Supervised student as first author)
[1] H.-M. Lam, F. Guo, H. Qiu, M. Zhang,H. Jiao*, and S. Zhang, “Pseudo Multi-Port SRAM Circuit for Image Processing in Display Drivers,”IEEE Transactions on Circuits and Systems for Video Technology, 2020.
[2] X. Huo^, C. Liao, M. Zhang,H. Jiao*, and S. Zhang, “A Pixel Circuit With Wide Data Voltage Range for OLEDoS Microdisplays With High Uniformity,”IEEE Transactions on Electron Devices, Vol. 66, No. 11, pp. 4798-4804, November 2019.
[3] Y. Sun, W. He, Z. Mao,H. Jiao*, and V. Kursun, “A High-Yield and Robust 9T SRAM Cell Tolerant to Removal of Metallic Carbon Nanotubes,”IEEE Transactions on Device and Materials Reliability, Vol. 17, No. 1, pp. 20-31, March 2017.
[4]H. Jiaoand V. Kursun, “Reactivation Noise Suppression with Sleep Signal Slew Rate Modulation in MTCMOS Circuits,”IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 21, No. 3, pp. 533-545, March 2013.
[5]H. Jiaoand V. Kursun, “Threshold Voltage Tuning for Faster Activation with Lower Noise in Tri-Mode MTCMOS Circuits,”IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 20, No. 4, pp. 741-745, April 2012.
[6]H. Jiaoand V. Kursun, “Ground Bouncing Noise Suppression Techniques for Data Preserving Sequential MTCMOS Circuits,”IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 19, No. 5, pp. 763-773, May 2011.
[7]H. Jiaoand V. Kursun, “Ground-Bouncing-Noise-Aware Combinational MTCMOS Circuits,”IEEE Transactions on Circuits and Systems I, Vol. 57, No. 8, pp. 2053-2065, August 2010.
►代表性国际会议论文(* Corresponding author; ^ Supervised student as first author)
[1]H. Jiaoand Z. Zhang, “A Compact Low-Power Data Retention Flip-Flop with Easy-Sleep Mode,”Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2020.
[2] P. Detterer^, C. Erdin, J. Huisken,H. Jiao, M. Nabi, T. Basten, J. Pineda de Gyvez, “Trading Sensitivity for Power in an IEEE 802.15.4 Conformant Adequate Demodulator,”Proceedings of the IEEE/ACM Conference on Design, Automation and Test in Europe (DATE), March 2020.
[3] K. Singh^, B. de Bruin, J. Huisken,H. Jiao, and J. Pineda de Gyvez, “Voltage Stacked Design of a Microcontroller for Near/Sub-threshold Operation,”Proceedings of the IEEE International SoC Conference (SOCC), pp. 370-375, September 2019.
[4] X. Huo^, W. Bai, H.-M. Lam, C. Liao, M. Zhang, S. Zhang, andH. Jiao*, “A Compact Low-Voltage Segmented D/A Converter with Adjustable Gamma Coefficient for AMOLED Displays,”Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, May 2019.
[5] P. Detterer^, C. Erdin, M. Nabi, J. Pineda de Gyvez, T. Basten, andH. Jiao*, “Trading Digital Accuracy for Power in an RSSI Computation of a Sensor Network Transceiver,”Proceedings of the IEEE/ACM Conference on Design, Automation and Test in Europe (DATE), pp. 102-107, March 2019.
[6] L. Katselas^, A. Hatzopoulos,H. Jiao, C. Papameletis, and E. J. Marinissen, “Embedded Toggle Generator to Provide Realistic Test Conditions during Test of Digital 2D-SoCs and 3D-SICs,”Proceedings of the IEEE International Test Conference (ITC), pp. 1-9, October 2018.
[7] F. Hu^, M. Zhang, andH. Jiao*, “Achieving Low Power Classification with Classifier Ensemble,”Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 16-21, July 2018.
[8] Y. Li^, M. Shao,H. Jiao, A. Cron, S. Bhatia, and E. J. Marinissen, “IEEE Std P1838’s Flexible Parallel Port and its Specification with Google’s Protocol Buffers,”Proceedings of the IEEE European Test Symposium (ETS), pp. 1-6, May 2018.
[9] K. Singh^, O. A. Rodriguez Rosas,H. Jiao, J. Huisken, and J. Pineda de Gyvez, “Multi-Bit Pulsed-Latch Based Low Power Synchronous Circuit Design,”Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, May 2018.
[10] K. Singh^,H. Jiao, J. Huisken, H. Fatemi, and J. Pineda de Gyvez, “Low Power Latch Based Design with Smart Retiming,”Proceedings of the IEEE/ACM International Symposium on Quality Electronic Design (ISQED), pp. 329-334, March 2018.
[11] M. van Leussen^, J. Huisken, L. Wang,H. Jiao*, and J. Pineda de Gyvez, “Reconfigurable Support Vector Machine Classifier with Approximate Computing,”Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2017.
[12] H. Ahmadi Balef^,H. Jiao, J. Pineda de Gyvez, and K. Goossens, “An Analytical Model for Interdependent Setup/Hold-Time Characterization of Flip-flops,”Proceedings of the IEEE/ACM International Symposium on Quality Electronic Design (ISQED), pp. 209-214, March 2017.
[13] E. J. Marinissen, T. McLaurin, andH. Jiao, “IEEE Std P1838: DfT Standard-under-Development for 2.5D-, 3D-, and 5.5D-SICs,”Proceedings of the IEEE European Test Symposium (ETS), May 2016.
[14] Y. Sun,H. Jiao, and V. Kursun, “Low-Leakage 9-CN-MOSFET SRAM Cell with Enhanced Read and Write Voltage Margins,”Proceedings of the IEEE International Conference on Microelectronics (ICM), pp. 164-167, December 2014 (Best Paper Award).
[15]H. Jiaoand V. Kursun, “Ground Gated 8T SRAM Cells with Enhanced Read and Hold Data Stability,”Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 52-57, August 2013.
[16] S. M. Salahuddin,H. Jiao, and V. Kursun, “A Novel 6T SRAM Cell with Asymmetrically Gate Underlap Engineered FinFETs for Enhanced Read Data Stability and Write Ability,”Proceedings of the IEEE/ACM International Symposium on Quality Electronic Design (ISQED), pp. 353-358, March 2013.
[17]H. Jiaoand V. Kursun, “Multi-Phase Sleep Signal Modulation for Mode Transition Noise Mitigation in MTCMOS Circuits,”Proceedings of the IEEE International SoC Design Conference (ISOCC), pp. 466-469, November 2012 (SoC Design Group Award).
[18]H. Jiaoand V. Kursun, “Sleep Signal Slew Rate Modulation for Mode Transition Noise Suppression in Ground Gated Integrated Circuits,”Proceedings of the IEEE International SoC Conference (SOCC), pp. 365-370, September 2011.
