1) Hui Sun, Meihua Liu, Peng Liu, Xinnan Lin*, Xiaole Cui, Jianguo Chen, Dongmin Chen*,Performance optimization of lateral AlGaN/GaN HEMTs with cap gate on 150-mm silicon substrate, Solid-State Electronics,dx.doi.org/10.1016/j.sse.2017.01.006:28-32.
2) Wei Chen, Kaiwen Li, Yao Wang, Xiyuan Feng, Zhenwu Liao, Qicong Su, Xinnan Lin*, Zhubing He*, Black Phosphorus Quantum Dots for Hole Extraction of Typical Planar Hybrid Perovskite Solar Cells, J. Phys. Chem. Lett., DOI: 10.1021/acs.jpclett.6b02843, 591-598.
3) Ying Xiao, Xinnan Lin*, Haijun Lou*, Baili Zhang , Lining Zhang, Mansun Chan,”A Short Channel Double -Gate Junctionless Transistor Model Including the Dynamic Channel Boundary Effect”, IEEE TRANSACTION ELECTRON DEVICES, 2016, 63(12):4661-4667.
4) “Hongyu He, Yuan Liu, Binghui Yan, Xinnan Lin, Shengdong Zhang, “Analytical Drain Current Model for Organic Thin-Film Transistors at Different Temperatures Considering Both Deep and Tail Trap States”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL.63,NO.11: 4423--4431.
5) Yunpeng Dong, Lining Zhang*, Xiangbin Li, Xinnan Lin*, Mansun Chan*, A Compact Model for Double-Gate Heterojunction Tunnel FETs, IEEE Transactions on Electron Devices, VOL.63,NO.11: 4506-4513.
6) Ying Xiao, Baili Zhang, Haijun Lou*, Lining Zhang, and Xinnan Lin*. A Compact Model of Subthreshold Current With Source/Drain Depletion Effect for the Short-Channel Junctionless Cylindrical Surrounding-Gate MOSFETs, IEEE Transactions on Electron Devices, 2016, 63(5):2176-2181.
7) Xinnan Lin*, Baili Zhang, Ying Xiao, Haijun Lou*, Lining Zhang*, and Mansun Chan. Analytical Current Model for Long-Channel Junctionless Double-Gate MOSFETs, IEEE Transactions on Electron Devices, 2016, 63(3):959-965.
8) Chenyue Ma, Lining Zhang*, Xinnan Lin*, Mansun Chan, Universal framework for temperature dependence prediction of the negative bias temperature instability based in microscope pictures, Japanese Journal of Applied Physics, 55(4):044201 1-6,April 2016.
9) Dan Li, Baili ZhangA, Haijun Lou, Lining Zhang, Xinnan Lin, and Mansun Chan, Comparative Analysis of Carriers Statistics on MOSFET and Tunneling FET Characteristics, IEEE JEDS, vol 3,No 6, Nov. 2015, 447-451.
10) Haijun Lou, Baili Zhang, Dan Li, Xinnan Lin*, Jin He* and Mansun Chan, “Suppression of subthreshold characteristics variation for junctionless multigate transistors using high-k spacers”, Semicond. Sci. Technol. 30 (2015) 015008 (7pp).
11) Jian Chen, Hang Meng, Frank X.C.Jiang, Xinnan Lin*, A Snapback-Free Shorted-Anode Insulated Gate Bipolar Transistor with an N-path Structure, Superlattices and Microstructures, 2015:201-209.
12) Yihan Chen, Kit Chu Kwong, Xinnan Lin*, Zhitang Song, and Mansun Chan*, 3-D Resistance Model for Phase-Change Memory Cell, IEEE TRANSACTIONS ON ELECTRON DEVICES, 2014/Vol 61, 4098-4104.
13) Haijun Lou, Dan Li, Yan Dong, Xinnan Lin*, JinHe*, Shengqi Yang and Mansun Chan, Suppression of tunneling leakage current in junctionless nanowire transistors, Semicond. Sci. Technol. 28 (2013) 125016 (6pp).
14) Haijun Lou, Dan Li, Yan Dong, Xinnan Lin*, Shengqi Yang, Jin He*, and Mansun Chan, Effects of Fin Sidewall Angle on Subthreshold Characteristics of Junctionless Multigate Transistors, Japanese Journal of Applied Physics 52 (2013) 104302.
15) Li Binghua, Frank X. C. Jiang, Li Zhigui, Lin Xinnan*, A trench accumulation layer controlled insulated gate bipolar transistor with a semi-SJ structure, Journal of Semiconductors, 2013/Vol.34/No.12.
16) Lining Zhang, Xinnan Lin*, Jin He*, and Mansun Chan*, "An Analytical Charge Model for Double-Gate Tunnel FETs", IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 12, DECEMBER 2012.
17) Wei Yiqun, Lin Xinnan*, Jia Yuchao, Cui Xiaole,Zhang Xing and Song Zhitang, Contact size scaling of a W-contact phase-change memory cell based on numerical simulation, Journal of Semiconductors, VOL.33, NO.11,November 2012, 114006- 1-5.
18) Wei Yiqun, Lin Xinnan*, Jia Yuchao, Cui Xiaole,He Jin, Zhang Xing, A SPICE model for a phase-change memory cell based on the analytical conductivity model, Journal of Semiconductors, VOL.33, NO.11,November 2012, 114004- 1-5.
19) Haijun Lou, Lining Zhang, Yunxi Zhu, Xinnan Lin*, Shengqi Yang, Jin He* and Mansun Chan, “A Junctionless Nanowire Transistor With Dual-Material-Gate”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 7, JULY 2012, PP 1829~1836.
20) Lin Li, Lining Zhang, Xinnan Lin*, Jin He, Chi On Chui and Mansun Chan*, Phase-Change Memory with Multi-Fin Thin-Film-Transistor Driver Technology,IEEE Electron Device Letters, VOL. 33, NO. 3, MARCH 2012,405-407.
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